DLD MID2 

1.	16 inputs ,40 AND gates,100 OR gates are in a PLA . The number of fuses to be programmed is :->5380 

2.	8 RAM chips of 16X4 size have their busses such that the data bus is 16 bits wide. This system memory size is :->64K X 8 

3.	A binary counter makes use of --------------- flipflops. :->T 

4.	A binar y number can be multiplied by 2 or divided by 2 with help of :->shift register 

5.	A capacity of a PLA is specified in terms of :->Number of inputs and product term, and outputs 

6.	A circuit consists of m flipflops, it generates ---------------- states. :->2m 
7.	A control subsystem consists of :->essentially sequential circuits 
8.	A counter that does not use any additional logic gate is---------------. :->Presettable counter 

9.	A decision box in an asm chart :->has two exit paths 

10.	A Finite State Machine :->is same as a clocked sequent ial circuit 

11.	A finite state machine :->same as clocked sequential circuits 

12.	A five bit binary counter uses flip flops with propagation delay time of 10 nS each. The maximum possible time required for change of state will be :->50 nS 
13.	A flip flop which responds to a falling edge is referred as :->Negative Edge triggered 
14.	A FPLA can :->can be programmed by user only once 

15.	A fu nctio n table is requ ired in ver y large numbers. The memor y mo st su itable for this purpo se is :-> 

16O. MA johnson counter is also called as---------------------. :->Inverse feedback counter

17.	A latch can be :->D flip flop 

18.	A machine po ssessing the pro perties that is a :->moore machine 

19.	A n-bit binary counter with n flipflops can count from-------------------. :->0 to 2 

20.	A pattern of gates fabricated on an area of silicon that is repeated thousands of times until the chip is covered with 

identical elements is called :->Gate Array 

21.	A PLA consists of :->AND, OR and invert/ non invert matrix 

22.	A PLA is :->a LSI device 

23.	A PLA is a :->Mask programmable 

24.	A program table is used for :->PLA's 

25.	A Programmable Logic Array has 32 inputs.It has to be programmed with 50 product terms and have 20 outputs. What is the number of fuses to be programmed :->3200 
26.	A PROM :->Can be programmed only once 
27.	A ring counter consisting of 6 flip flops will have :->6 states 

28.	A ring counter is one in which :->Only one flipflop is set while all the others are cleared. 

29.	A ring counter is same as --------------- counter. :->parallel 

30.	A ring counter is useful in generating ----------------. :->Timing signals 

31.	A ROM has 16 address lines and 8 data lines. It is organized as :->64K X 8 

32.	A ROM has 16 bit address bus. The number of locations in this memory is :->65536 
33.	A ROM has 32K X 8 organisation. Its capacity in bits is :->256K bits 
34.	A sequential circuit does not use clock pulses. It is :->an Asynchronous Sequential circuit 

35.	A sequential circuit is a combination of a combinational circuit and a --------------. :->Memory element 

36.	A sequential circuit with 06 states requires :->3 flip flops 

37.	A sequential circuit with 10 states will have :->4 Flip-Flops 

38.	A sequential circuit with a 4 numbers of outputs produces an output set containing :->16 sets 

39.	A sequential circuit with m flipflops and n inputs needs ---------- rows in the state table. :->2 

40.	A sequential machine is :->quintuple 
41.	A serial Adder is a :->a sequential and combinational circuit 

42.	A shift register becomes a ring counter if -----------------. :->output of the last flipflop is connected to the input of first flipflop. 
43.	A single literal term in S O P expression :->requires an AND gat e for PLA implementation 

44.	A state box in an asm chart :->is included only in one asm block 

45.	A switching function Y can be deco mposed into two thresho ld functions f1 and f2 . The fu nction Y can be implemented using :->2 threshold elements interconnected to perform OR operations 

46.	A switching function Y vcan be deco mposed into two thresho ld functions f1 and f2 . The function Y can be implemented using :->2 threshold elements interconnected to perform OR operation 

47.	A synchronous sequential circuit can be described by :->state diagram or table or ASM chart 

48.	A threshold function :->is always a unite function 

49.	A threshold function has 3 minimal true vertices and 3 maximal false vertices. The number of inequalities to be satisfied are :->9 

50.	A threshold function has a 3 minimal true vertices and 3 maximal false vertices. The number of inequalities to be satisfied are :->9 
51.	A twisted ring counter consisting of six Flip Flops will have :->12 states 
52.	A twisted ring counter having four flip flops has :->32 states 

53.	A Unate function may be :->positive or negative in any combination of its variables 

54.	Advantages of threshold lo gic over conventional logic is :->less components and simple connections 

55.	all the operations specified within one ASM block must occur in synchronism during :->same clock pulse 

56.	An algorithmic state machine consists of :->combinational circuits and flip-flops 

57.	An Algorithmic State machine is same as :->synchronous clocked sequential finite state machine 

58.	An ASM chart can be :->converted t o a state diagram & table and implemented as a Flip-Flop 
59.	An ASM chart can be implemented using Flip-Flo ps and :->Gates,Multiplexors & PLD`s 
60.	An ASM Chart consists of :->state, decision and conditional output boxes 

61.	An asm chart of the mealy model :->contains conditional output box 
62.	asm chart represents :->Synchronous sequential circuits 
63.	Distinguishing sequence for states A and B :->01 
64.	Distinguishing sequence for states A and F :->1011 
65.	Distinguishing sequence for states B and C :->001 
66.	Distinguishing sequence for states G and F :->1 
67.	For a 8 state machine if P4 = (A) (B) (CD) (EFG) (H) then its P3 part it ion ma y be :- >(CD)(A) (B) (EFG)(H) 
68.	For a 8 state machine if P4 = (AB) (CD) (EFH) (G) then its P3 partition may be :->(ABG)(CD) (EFH) 
69.	For designing a four variable combinational circuit a designer must use :->ROM with at least 16 locations 
70.	For designing a FSM ,K-maps can be used for minimizing the :->excitation and output logic 
71.	For PAL de sig n o f a log ic circ uit a sing le l iter al t erm :-> requires an AND gate and one input for OR gate 
72.	Four RAM chips of 16X4 size have their busses connected together. This system will be of size :->16X16 
73.	Fusible link is associated with :->P R O M 
74.	If _ _ _ _ _ _ _ _ is zero the following state is compatible with B :->C and B 
75.	If _ _ _ _ _ _ is zero then which of the following states is compatible with D :->B and C 
76.	If 2K timing signals are generated by a Johnson counter then it is a ---------------. :->K bit Johnson counter. 

77.	If a counter is connected using 5 flipflops then the max number of states that the 

counter can count are-----------. :->128

78.	If a ROM is organized as 16 bit words and contains 256 words then the capacity of the ROM is 2048 bits, the number of 4 bit wide words is :->4096 
79.	If a ROM is to be organized as 4 bit words and it contains 2048 bits , the number of 4 bit wide words is :->512 
80.	If an input sequence y -takes a machine from state A to state B then B is said to be A`s :-> - successor 

81.	If n is the number of states in a machine M and A and B are two distinguishable then they are distinguishable by a sequence of :->(n-1) or less 

82.	If t = setup time , t = propagation delay time,t = next state decoder delay, then maximum frequency of edge triggered flip flop is :->1/( t+ t+t) 
83.	If the dashes are replaced by 0ï¿½s the following state is the equivalent state :->AB 

84.	If the Mealy machine has K states and the outputs are binary then an equivalent Moore machine will have :->atmost 2K states 
85.	If w1 = -1 , w2 = - 1 & T= - 1.5 with binary inputs x1 & x2. The output Y represents :->NOR gate 

86.	If w1 =1 , w2 = 1 & T= 2 with binary inputs x1 & x2. The output Y represents :->AND gate 

87.	If we chose dashes as 0 which of these states is equivalent :->B CD 

88.	In a 4 bit shift right ring counter if the present state is 1000, then the next state is--------.:->0100 

89.	in a binary multiplier :->The partial product in A & multiplier in Q are both shifted to the left 

90.	In a binary multiplier after the shift operatio n :->one bit of partial product is transferred to Q 
91.	in a binary mu ltiplier the partial product is shifted :->left 

92.	In a combinational circuit the output at any instant depends on------------. :->Only input present at that instant of time 
93.	In a control system the number of flip flops used per state is :->1 

94.	In a control unit the next state is determined by :->gates 

95.	in a control unit the states are held in :->flip flops 

96.	In a counter consisting of four JK flip Flops , all the Flip Flops get triggered simultaneously. This counter circuit is 

:- 
>is a synchronous circuit 
97.	In a flipflop, the preset and clear inputs are used for making the output(q)--. :->q = 1 and 0 respectively 

98.	In a mealy model, the output is a function of :->neither present states nor external inputs 

99.	In a merger table compatibility is indicated by :->Correct 

100.	In a n RS flipflop when R=0 and S=0 the outputs are------------------------. :->Same as previous outputs 

101.	In a o ne flip-flop per state method the Boolean fu nctio n fo r setting the flip-flop is determined by :- 

>present state,input condition on directed line

102.	In a sequential circuit design state reduction is done for designing the circuit with :->minimum number of FlipFlops 

103.	In a sequential circuit the output at any instant depends on-------------------. :->On the past outputs and inputs present at that instant of 

time 

104.	In a T filpflop when t =1 the output ---------------------. :->Toggles 

105.	In an ASM Chart , Moore type of Outputs are represented by :->writing these outputs inside state box 

106.	In ASM chart Mealy type of outputs :->can be represented by writing output state variables inside state box 

107.	In converting JK flipflop to T flipflop, T input in terms of J,K and the output y is------.:->Jyï¿½+Ky 
108.	In general Merger table is preferred over merger graph when the number of states are:->Large 
109.	In serial adders the carry out of the Full Adder is given to :->D Flip Flop 

110.	Johnson counter is also known as :->Shift counter 

111.	Master Flip Flop is :->Pulse triggered 

112.	Maximu m co mpatibility class is a compatible which is :->not a subset of any other compatible 

113.	Mealy type of outputs are :->depend on present state and input 

114.	Minimisatio n of nu mber o f states redu ce the :->cost,number of gates, & complexity 

115.	Moore Type of Outputs are :->independent of the inputs 
116.	Race aro und condition occur s in JK Flip-Flops when :->both the inputs are 1 
117.	ROM available at hand are 16X4 in size. It is desired to have 64X8 ROM. The number of 16X4 roms to achieve 

this

are :->8

118.	S(t+1) is determined by s(t) and present inputs x(t) in which of the following machines:->ealy machine 

119.	Sequential circu its are classified in :->Two Ways 

120.	Serial adder can be designed using :->as a sequential circuit 
121.	Serial adder s are used because :->need less number of devices 
122.	Serial adder s contain the fo llowing logic compo nents :->gates , Flip-Flops and clocks 

123.	The address bus width of a ROM of size 1024X8bits is :->10 bits 

124.	The applications like ser ial to parallel converters, delay lines use :->Asynchronous counters 

125.	The binary multiplier consists of :->counters,registers,para llel adders 

126.	The characteristic equation of a RS flip Flop is :->S +R/Q 

127.	The clocked sequential circuit compared with asynchronous sequential circuit has :->Flip Flops & Clock 

128.	The compatibility o f two states in the merger table can be ind icated by :->Tick mark 
129.	The complete classes in co lumn B are :->CEF,CDE,BC 
130.	The complete classes in co lumn C are :->CDE & CEF 

131.	The complete classes in co lumn D are :->EF 

132.	The complete classes in co lumn E are :->EF 

133.	The control system of a digital system is :->sequential circuit 

134.	The data bus width of a 2048X8 ROM is :->8 

135.	The Decoder has :->fixed OR and AND gates 

136.	The design of a Clo cked sequential circuit requires :->requires the state assignment, reduction and the next 

state decoder 

137.	The design of a clocked sequential circuit requires :->the design of next decoder 

138.	The examp le o f a Mealy machine is :->Binary Counter 

139.	The examp le o f a Moo re machine is :->Sequence det ector 

140.	The flipflop can store---------------------------. :->One bit of data 

141.	The flipflops used in counters are-------------------. :->JK 
142.	The flipflops used in shift registers are-------------------. :->D 
143.	The following states are compatible with `A' if dash is `0' :->E 
144.	The memory element of a sequential circuit consists of-----------------. :->Only flipflops 

148.	The non Uniqueness of incompletely specified machines is that the equivalence partition consists of disjoint block, while the subsets of Compatibles may be :->Overlap ping 

149.	The number of directed arcs emanating from any state in a state diagram is :->2n , where n is the number of inputs 

150.	The number of directed arcs terminating on any state in a state diagram is :->independent of the number of inputs 

151.	The number of flipflops for a synchronous circuit is determined by-------------. :->The number of states needed 
in 
the circuit 
152.	The number of flipflops in a decade counter are---------------. :->4 
153.	The number of flipflops in a mod-N counter are-----------------. :->log2(N) 
154.	The number of multiplexers needed to design the control logic of a 4 state problem is :->2 
155.	The number of outputs of a threshold element is :->1 
156.	The output in a D flipflop is----------------- when clock is present. :->Same as D 
157.	The output of a clocked sequential circuit is independent of the input. This circuit can be represented by :->Moore  Model 

158.	The output of a clocked sequential circuit is independent of the input. This circuit can be represented by the :->Moore model 

159.	The output Qn of a JK Flip Flop is 1. It changes to 0 when a clock pulse is applied. The inputs Jn & Kn are r espectively :->1 and X 
160.	The parameters of a threshold element are :->weights assigned to input variables and T