3.	Primary Memory		
				4.	Magnetic Tape		
1.	"Locality of Reference" is related to: [01D01]	11.	In the Memory Hierarchy, Speed of accessing is high for		
						
	1.	Register		[01S04]			
							
	2.	Cache		1.	Register		
							
	3.	Primary Memory		2.	Cache		
							
	4.	Magnetic Tape		3.	Primary Memory		
							
2.	Expand CAM [01D02]		4.	Magnetic Tape		
						
	1.	Cache Access Memory	12.	In the Memory Hierarchy, Speed of accessing is low for		
							
	2.	Call Access Mode		[01S05]			
							
	3.	Contents  Addressable  Memory		1.	Register		
							
	4.	Cache Access Module		2.	Cache		
3.	Associative Memory  is like [01D03]		3.	Primary Memory		
							
	1.	Primary Memory		4.	Magnetic  Tape		
	2.	Secondary Memory	13.	In the following which is accesed sequentially  [01S06]		
						
	3.	Cache Memory		1.	Register		
							
	4.	Auxiliary Memory		2.	Cache		
							
4.	In the Memory Hierarchy, top to bottom (Registers to		3.	Primary Memory		
							
	Tape) [01M01]		4.	Magnetic  Tape		
							
	1.	Capacity Decreases	14.	In the Memory Hierarchy, Cost per bit is least for		
						
	2.	Capacity  Increases		[01S07]			
	3.	Speed Increases		1.	Register		
	4.	Cost per bit Increases		2.	Cache		
5.	In the Memory Hierarchy, top to bottom (Registers to		3.	Primary Memory		
							
	Tape) [01M02]		4.	Magnetic  Tape		
							
	1.	Cost per bit  decreases	15.	In the Memory Hierarchy, the Cost per bit is most for		
						
	2.	Cost per bit Increases		[01S08]			
							
	3.	Speed Increases		1.	Register		
							
	4.	Access Time Decreases		2.	Cache		
							
6.	In the Memory Hierarchy, bottom to top (Tape to		3.	Primary Memory		
							
	Registers) [01M03]		4.	Magnetic Tape		
	1.	Speed Decreases	16.	512 x 8 ROM  indicates [02D01]		
						
	2.	Access time Increases		1.	512 data, 8 address lines		
							
	3.	Capacity Increases		2.	512  address,  8  data lines		
							
	4.	Capacity  Decreases		3.	520 address lines		
							
7.	In the Memory Hierarchy, top to bottom (Registers to		4.	520 data lines		
							
	tape) [01M04]	17.	The Static  RAM  consists of [02M01]		
						
	1.	Speed Increases		1.	Capacitors		
	2.	Speed decreases		2.	Internal Flip Flops		
	3.	Cost per bit Increases		3.	Internal Caches		
							
	4.	Access time decreases		4.	Filters		
							
8.	In the Memory Hierarchy, the following Memory has	18.	The Dynamic RAM  consists of [02M02]		
						
	least capacity  [01S01]		1.	Capacitors		
							
	1.	Register		2.	Internal Flip Flops		
	2.	Cache		3.	Internal Caches		
							
	3.	Primary Memory		4.	Filters		
	4.	Magnetic Tape	19.	The decoder used for decoding 512 x 8 ROM  consists of		
9.	In the Memory Hierarchy, the following Memory has		how many input lines? [02S01]		
	maximum Access time [01S02]		1.	512		
							
	1.	Register		2.	8		
							
	2.	Cache		3.	9		
	3.	Primary Memory					
				4.	520		
	4.	Magnetic  Tape					
			20.	The Principal technology used for main Memory is based		
10.	In the Memory Hierarchy, the following Memory has				
			on [02S02]		
	least Access time [01S03]				
			1.	Semi conductor ICs		
	1.	Register					
				2.	Conductor  ICs		
	2.	Cache					
				3.	Both Semi Conductor and Conductor ICs		

WORD BLOCK FRAME

4.	Using Insulator 

21.	Refreshing is required for [02S03] 

1.	All RAMs 

2.	Only DRAMs 

3.	Only SRAMs 

4.	Both SRAMs and DRAMs 

22.	Boot Strap loader requires [02S04] 

1.	RAM 

2.	ROM 

3.	Any Memory 

4.	Only Processor 

23.	By making programs and data available at a rapid rate, it is possible to [03D01] 

1.	Decrease the performance 

2.	Increase  the performance 

3.	Save Memory 

4.	Reduce cost 

24.	The part of the computer system that supervises the flow of information between Auxiliary Memory and Main Memory is called [03D02] 

1.	Processor Management  System 

2.	Data Management System 

3.	Address Management  System 

4.	Memory Management System 

25.	Existence of two or more programs in different parts of the Memory Hierarchy at the same time is defined as: [03M01] 

1.	Uni programming 

2.	Multi programming 

3.	Multi processing 

4.	Uni processing 

26.	If Cache Access time is 100ns, Memory  access time is	
	1000ns, if the hit percentage is 100 %, what is the	
	Average  access time [03M02]	

1.	100 

2.	1000 

3.	1100 

4.	10 

27.	If both Cache Memory and Main Memory are updated for a write operation, the type of the Cache Memory is called [03M03] 

1.	Write-back 

2.	Write-through 

3.	Associative 

4.	TLB 

28.	If only Cache location is updated during a Write operation as long as there is no replacement, the type of the Cache Memory is called [03M04] 

1.	Write-back 

2.	Write-through 

3.	Associative 

4.	TLB 

29.	Replacing the block that has been not used for the longest period of time is [03M05] 

1.	FIFO 

2.	LRU 

3.	MRU 

4.	LFU 

30.	Replacing the page that entered the Memory at first is [03M06] 

1.	FIFO 

2.	LRU 

3.	MRU 

4.	LFU 

31.	A faster and smaller Memory in between CPU and main Memory is [03S01] 

1.	Primary Memory 

2.	Secondary Memory 

3.	Cache Memory 

4.	Auxiliary Memory 

32.	To compensate speed mismatch between main Memory and Processor, the Memory used is [03S02] 

1.	Primary Memory 

2.	Secondary Memory 

3.	Cache Memory 

4.	Auxiliary Memory 

33.	If Hit  ratio is 0.8, the miss ratio [03S03] 

1.	9.2 

2.	92 % 

3.	0.2 

4.	20 % 

34.	In the following, which is not a Cache Mapping technique [03S04] 

1.	Associative Mapping 

2.	Direct Mapping 

3.	Test-Associative  Mapping 

4.	Set-Associative Mapping 

35.	In four-way Set-Associative mapping, the number of tags are [03S05] 

1.	One 

2.	Two 

3.	Four 

4.	Sixteen 

36.	In the following, which is the fastest mapping technique [03S06] 

1.	Direct Mapping 

2.	Associative  Mapping 

3.	Test-Associative Mapping 

4.	Set-Associative Mapping 

37.	In Cache, the data stored is [03S07] 

1.	Most frequently  used 

2.	Least frequently  used 

3.	Never used 

4.	Segment with large data 

38.	The transfer of data between main Memory and Cache is [03S08] 

1.	WORD 

2.	BLOCK 

3.	LINE 

4.	CHARACTER 

39. The transfer of data between Processor and Cache is [03S09]

1.

2.

3.

4.	CHARACTER 

40.	"Beladys Anomaly"  does not  occur in [04D01] 

1.	FIFO 

2.	LRU 

3.	MRU 

4.	Optimal  replacement 

41.	In Paging technique, the logical address  space is [04M01] 

1.	Divided into  equal parts 

2.	Divided into unequal parts 

3.	divided into two parts 

4.	Either equal or unequal parts 

42.	The technique of Segmentation	suffers which	
	fragmentation [04M02]		

1.	Internal 

2.	External 

3.	both Internal and External 

4.	Neither Internal nor External 

43.	"Paged Segmentation" has [04M03] 

1.	Internal fragmentation 

2.	External fragmentation 

3.	Zero fragmentation 

4.	Neither Internal nor External 

44.	The time taken to access a particular track is [04S01] 

1.	Seek time 

2.	Latency time 

3.	Access time 

4.	Burst time 

45.	The time taken to access a particular  sector is [04S02] 

1.	Seek time 

2.	Latency  time 

3.	Access time 

4.	Burst time 

46.	For a magnetic tape, the access is [04S03] 

1.	Random Access 

2.	Sequential  Access 

3.	Both Random and Sequential 

4.	Rotational 

47.	For a magnetic  disc, the access is [04S04] 

1.	Direct Access 

2.	Sequential Access 

3.	Both Random and Sequential 

4.	Rotational 

48.	The technique of Paging suffers which fragmentation [04S05] 

1.	Internal 

2.	External 

3.	both Internal and External 

4.	Neither Internal nor External 

49.	By using  TLB in Paged segmentation  [05D01] 

1.	Access  time decreases 

2.	Access time increases 

3.	Speed decreases 

4.	Fragmentation decreases 

50.	Contents addressable Memory (CAM) is related to [05D02] 

1.	Page table 

2.	Associative  Page  table 

3.	Inverted Page table 

4.	Normal Page table 

51.	If there are sixteen bits in the Virtual Address format, the size of the Virtual Address is [05M01] 

1.	16K words 

2.	16 words 

3.	64  K words 

4.	16M words 

52.	If the size of the Page is 1K for a Virtual Address space of 16K, the size of the Frame in main Memory is [05M02] 

1.	16K 

2.	8K 

3.	4K 

4.	1  K 

53.	Discs that are permanently attached to the unit assembly and cannot be removed by the occasional user are called [05S01] 

1.	Floppy discs 

2.	Hard  discs 

3.	External discs 

4.	Flash Memory 

54.	A disk drive with a removable disk is [05S02] 

1.	Hard disk 

2.	Floppy disk 

3.	Permanent disk 

4.	Cache 

55.	In the following, which is not a Physical Memory  [05S03] 

1.	Primary Memory 

2.	Cache Memory 

3.	Flash Memory 

4.	Virtual Memory 

56.	Which Page Replacement technique is most efficient [05S04] 

1.	FIFO 

2.	LRU 

3.	MRU 

4.	LFU 

57.	Page table contains [05S05] 

1.	Starting address of Page 

2.	Page  no.,  Frame no. 

3.	Length of the page 

4.	Page no., Segment no. 

58.	Number of Printing Characters in ACSII code are [06D01] 

1.	128 

2.	94 

3.	34 

4.	8 

59.	Number of Non Printing Characters in ACSII code are [06D02] 

1.	128 

2.	94 

3.	34 

4.	8 

60.   ASCII code uses how many bits [06M01]

1.     5

2.     7

3.	8 

4.	9 

61.	The Cathode Ray Tube contains an electronic gun which can be deflected [06M02] 

1.	Only horizontally 

2.	Only vertically 

3.	Both horizontally  and vertically 

4.	Neither horizontally nor vertically 

62.	Input/Output devices connected to the computer are also called as [06S01] 

1.	Modems 

2.	Routers 

3.	Peripherals 

4.	Processors 

63.	Which of the following is not a Printer? [06S02] 

1.	Inkjet printer 

2.	Dot  Matrix 

3.	Laser Printer 

4.	Scanner 

64.	In the following which is sequentially  accessed [06S03] 

1.	Magnetic Disc 

2.	Magnetic  Tape 

3.	Flash Memory 

4.	Cache Memory 

65.	The command used to activate the peripheral and to inform it what to do is [07D01] 

1.	Control  command 

2.	Status command 

3.	Data output  command 

4.	Data input command 

66.	The command that causes the interface to respond by transferring data from the Bus into one of its registers is [07D02] 

1.	Control command 

2.	Status command 

3.	Data output  command 

4.	Data input command 

67.	The command used that causes the interface to receive an item of data from the peripheral and places it in its Buffer register is [07D03] 

1.	Control command 

2.	Status command 

3.	Data output  command 

4.	Data input  command 

68.	In Asynchronous data transfer, both sender and receiver accompany a control signal that is: [07M01] 

1.	Strobe 

2.	Hand  Shaking 

3.	Two wire control 

4.	Single wire control 

69.	The circuit which provides the interface between computer and similar interactive terminal is [07M02] 

1.	USRP 

2.	UART 

3.	Flip Flop 

4.	D-Flip Flop 

70.	The command used to test various status conditions in the interface and the peripheral is [07S01] 

1.	Control command 

2.	Status command 

3.	Data output  command 

4.	Data input command 

71.	In the following which mapping does not distinguish Memory address and I/O address [07S02] 

1.	Memory mapped I/O 

2.	Isolated I/O 

3.	Independent I/O 

4.	Interrupt  driven I/O 

72.	In the following which mapping uses different address space for Memory and I/O [07S03] 

1.	Memory mapped I/O 

2.	Isolated  I/O 

3.	Independent I/O 

4.	Interrupt  driven I/O 

73.	The rate at which Serial information is transmitted and is equivalent to the data transfer in bits per second is [07S04] 

1.	Baud rate 

2.	Bit rate 

3.	Control rate 

4.	Strobe rate 

74.	In Daisy chaining, the number of interrupt request lines is (are) [08D01] 

1.	n 

2.	2n 

3.	only one 

4.	changes 

75.	In Daisy chaining, the number of interrupt acknowledge lines is (are) [08D02] 

1.	n 

2.	2n 

3.	only one 

4.	changes 

76.	In the following, which is not priority interrupt method [08D03] 

1.	Polling 

2.	Daisy chaining 

3.	Parallel priority 

4.	Direct  Memory Access 

77.	In the following, which is efficient [08M01] 

1.	Programmed I/O 

2.	Interrupt initiated I/O 

3.	Direct  Memory Access 

4.	All the equally efficient 

78.	In the following, which uses separate controller for data transfer [08M02] 

1.	Programmed I/O 

2.	Interrupt initiated I/O 

3.	Direct Memory Access 

4.	Memory mapped I/O 

7 9.   In  Polling, the drawback is [08M03]

1.	Cost is more 

2.	Complex hardware is required 

3.	Time consuming 

4.	Maintenance is more 

80.	Daisy Chaining is [08M04] 

1.	Software method 

2.	Hardware method 

3.	Both software and hardware 

4.	Neither software nor hardware 

81.	In the following, which is not a mode of transfer [08S01] 

1.	Programmed I/O 

2.	Interrupt initiated I/O 

3.	Direct Memory Access 

4.	Memory mapped I/O 

82.	In Priority interrupt when two devices interrupt the computer at the same, the computer services the device [08S02] 

1.	with larger length at first 

2.	with shorter length at first 

3.	with highest  priority at first 

4.	with lowest priority at first 

83.	In Daisy chaining, device with highest priority is in [08S03] 

1.	First position 

2.	Middle position 

3.	Last position 

4.	Any position 

84.	Continuously monitoring I/O  devices is done in [08S04] 

1.	Programmed I/O 

2.	Interrupt initiated I/O 

3.	Direct Memory Access 

4.	Memory mapped I/O 

85.	In the following, which is more time consuming [08S05] 

1.	Programmed I/O 

2.	Interrupt initiated I/O 

3.	Direct Memory Access 

4.	Memory mapped I/O 

86.	A block sequence consisting of a number of Memory words is transferred continuously while a DMA controller is master of Memory Bus. This is [09D01] 

1.	Polling 

2.	Daisy Chaining 

3.	Burst transfer 

4.	Cycle Stealing 

87.	DMA controller transfer one data word at a time and transfers the control of the Bus to CPU. This is [09M01] 

1.	Polling 

2.	Daisy Chaining 

3.	Burst transfer 

4.	Cycle  Stealing 

88.	In the following, which is a method related to DMA. [09S01] 

1.	Polling 

2.	Daisy Chaining 

3.	Parallel Priority 

4.	Cycle  Stealing 

89.	For fast transfer of information between Magnetic Disc and Memory, which of the following is recommended [09S02] 

1.	Programmed I/O 

2.	Daisy Chaining 

3.	Polling 

4.	DMA 

90.	The DMA controller acts like [09S03] 

1.	Primary Memory 

2.	CPU 

3.	Cache Memory 

4.	Router 

91.	The number of basic I/O commands in IBM 370 computer IOP is [10D01] 

1.	50 

2.	6 

3.	8 

4.	40 

92.	The number of basic I/O commands in Intel 8089 computer IOP is [10D02] 

1.	50 

2.	6 

3.	8 

4.	40 

93.	The Intel 8089 I/O processor contains the IC package of [10M01] 

1.	64 pins 

2.	40  pins 

3.	16 pins 

4.	32 pins 

94.	A Processor  with Direct Memory Access capability  that	
	communicates with I/O  devices is [10S01]	

1.	Input  Output  Processor 

2.	Data communication processor 

3.	Data communication programmer 

4.	Input  Output  programmer 

95.	A processor that communicates with remote terminals over telephone and other communication media in a serial fashion is called [10S02] 

1.	Input  Output  Processor 

2.	Data communication processor 

3.	Data communication programmer 

4.	Input  Output  programmer 

96.	The I/O processor in IBM 370 computer is called [10S03] 

1.	Router 

2.	Channel 

3.	Device 

4.	Modem 

97.	Let the time taken to process a sub-operation in each segment be 20ns. Assume That the pipeline has 4 segments and executes 100 tasks in sequence. What is the Speed up of pipeline system? [11D01] 

1.	8000ns 

2.	3060ns 

3.	2060ns 

4.	6000ns 

98. The _ _ _ _ _ _ _ _ _ _ architecture represents the organization of a computer containing a single control unit, a processor unit and a memory unit. [11M01]

1.     SIMD

2.     MISD

3.	SISD 
4.	MIMD 

99.	Total operations performed going through all the segments in the pipeline is called as _ _ _ _ _ _ _ _ _ 

[11M02] 

1.	function 

2.	process 

3.	sequence 

4.	task 

100.One type of parallel processing that does not  fit Flynn	s	
classification is _ _ _ _ _ _ _ _ processing. [11M03]		
1.	array		
2.	vector		
3.	multi		
4.	pipeline		
101.The sequence of instructions  read from memory		
constitutes  _ _ _ _ _ _ _ _ [11S01]		
1.	data stream		
2.	execution stream		
3.	instruction stream		
4.	process stream		

102.Most of the multi processors and multi computer systems can be classified in _ _ _ _ _ _ _ _ category. [11S02]

1.     MISD

2.     SIMD

3.     SISD

4.     MIMD

103.The behavior of a pipeline can be illustrated with _ _ _ _

_ _ _ diagram [11S03]

1.	frequency-time 

2.	timing 

3.	space-time 

4.	dataflow 

104.	As the number of tasks increases, the speed up is equal to 

the number of _ _ _ _ _ _ in the pipeline [11S04]

1.	tasks	
2.	segments	
3.	suboperations	
4.	instructions.	

105.Suppose  the time delays of four segments are

and the interface registers have a delay of tr=10ns. What must be the clock cycle time? [12D01]

1.     100ns

2.     120ns

3.     110ns

4.     130ns

106.Each entry in the BTB consists of the address of a previously executed _ _ _ _ _ _ _ _ instruction and the _

_ _ _ _ _ _ _ instruction for that branch [12D02]

1.	branch, target 

2.	branch, buffer 

3.	target, branch 

4.	buffer, branch 

107._ _ _ _ _ _ _ _ _ conflicts arise when an instruction depends on the result of a previous instruction [12M01]

1.     resource

2.	branch 
3.	segment 

4.	data dependency 

108.When an overflow occurs, the mantissa of the sum or difference is shifted _ _ _ _ _ _ And exponent incremented by _ _ _ _ _ _ [12M02]

1.	right, one 

2.	left, one 

3.	right, two 

4.	left, two 

109.A _ _ _ _ _ _ _ _ pipeline divides an arithmetic operation into suboperations for execution in the pipeline segments. [12S01]

1.     vector

2.     arithmetic

3.     instruction

4.     multiple

110._ _ _ _ _ _ _ _ _ pipeline operates on a stream of instructions by overlapping phases of instruction cycle. [12S02]

1.     arithmetic

2.     instruction

3.     vector

4.     multiple

111.The instruction fetch segment can be implemented by means of a _ _ _ _ _ _ buffer [12S03]

1.     LIFO

2.     FIFO

3.     FILO

4.     LILO

112.The instruction stream queuing mechanism provides an efficient way for reducing _ _ _ _ _ _ _ _ _ _ for reading instructions from memory [12S04]

1.	access  time 

2.	seek time 

3.	overlapping time 

4.	processing time 

113._ _ _ _ _ _ _ _ _ is a circuit that detects instructions whose source operands are destinations of instructions further up in the pipeline [12S05]

1.	operand forwarding 

2.	interlocks 

3.	delayed load 

4.	data decoder 

114.The method used in most RISC processors is to rely on the compiler to redefine the branches so that they take effect at the proper time in the pipeline. This method is called _ _ _ _ _ _ _ _ _ _ [13D01]

1.	delayed  branch 

2.	delayed load 

3.	delayed store 

4.	delayed add 

115.The RISC consists of only _ _ _ _ _ _ _ _ length instruction format [13M01]

1.	variable 

2.	fixed 

3.	small number 

4.	large number 

116.The data transfer instructions  in RISC are limited to _ _

_ _ _ _ _ and _ _ _ _ _ _ _ _ instructions [13M02]

1.	add, sub	
2.	mul, div	
3.	load, store	
4.	in, out	

117.Since all operands are in registers, there is no need for _ _

_ _ _ _ _ _ of operands from memory [13S01]

1.	fetch	
2.	decode	
3.	execute	
4.	store	

118.The concept of delaying the use of the data loaded from memory is referred to as _ _ _ _ _ _ _ _ _ _ [13S02]

1.	delayed branch	
2.	delayed  load	
3.	delayed store	
4.	delayed add	

119.The compiler for a processor that uses delayed branches is designed to analyze the instructions _ _ _ _ _ _ _ _ _ _ _

the branch [13S03]

1.	before 

2.	after 

3.	before  &  after 

4.	later 

120.A computer capable of vector processing eliminates the overhead associated with the time it takes to _ _ _ _ _ _ _

_ and _ _ _ _ _ _ _ _ _ _ the instructions in the program loop [14D01]

1.	fetch, decode 

2.	fetch, execute 

3.	execute, decode 

4.	fetch, store 

121.	A  vector processor that uses an n-way interleaved memory 

can fetch _ _ _ _ _ _ _ _ _ _ _ operands from _ _ _ _ _ _

_ _ _ different modules [14D02]

1.	n,  n	
2.	n, m	
3.	1, 1	
4.	1, 2	

122.Matrix _ _ _ _ _ _ _ is one of the most computational intensive operations performed In computers with vector processors [14M01]

1.	addition	
2.	subtraction	
3.	transpose	
4.	multiplication	

123.A computer with vector instructions and pipelined floating-point arithmetic operations is referred to as _ _ _

_ _ _ _ _ computer [14M02] 1. mini

2.     mainframe

3.     super

4.     micro

124.A measure used to evaluate computers in their ability to performs a given number of floating-point operations per second is referred as _ _ _ _ _ _ _ _ _ _ [14M03]

1.     MIPS

2.     KIPS

3.     FLOPS

4.     BAUDS

125._ _ _ _ _ _ _ _ _ _ processing deals with computations involving large matrices [14S01]

1.     arithmetic

2.     parallel

3.     pipeline

4.     vector

126.Aerodynamics and space flight  simulations  uses _ _ _ _ _

_ _ _ _ _ processing [14S02] 1. vector

2.     arithmetic

3.     parallel

4.     pipeline

127.In _ _ _ _ _ _ _ memory, different sets of addresses are assigned to different memory modules [14S03]

1.     associate

2.     random

3.     interleaved

4.     multiple

128.A vector is an ordered set of _ _ _ _ _ _ _ _ _ dimensional array of data items [14S04]

1.     two

2.     three

3.     one

4.     four

129.Instruction format for vector instruction is _ _ _ _ _ _ _ _

address instruction [14S05] 1. zero

2.     one

3.     two

4.     three

130.One of the following _ _ _ _ _ _ _ _ _ system is an example for array processor [15D01]

1.	VAX	
2.	PDP-11	
3.	MPP	
4.	ILLIAC-IV	

131.Each processing element  of SIMD will have _ _ _ _ _ _ _

_ _ memory [15D02]

1.	global	
2.	shared	
3.	local	
4.	temporary	
132.An array processor consists of _ _ _ _ _ _ _ _ _	
instructions and _ _ _ _ _ _ _ data organization [15M01]	
1.	single,  multiple	
2.	multiple, single	
3.	single, single	
4.	multiple, multiple	

133.The objective of the attached array processors is to provide _ _ _ _ _ _ _ _ capabilities to a conventional computer [15M02]

1.	high speed 

2.	pipelined 

3.	parallel