[DLD-MID-I]

1)	1.The number of zero bits precede the binary number will = Ans:-does not change its value 
2)	Group of four bits are called Ans:-nibbles 
3)	Group of sixteen bits are called Ans:- words 

4)	The byte can represent signed numbers in the range of = Ans: --128 .....+127 
5)	Inside today's computers, data is represent ed as Ans:-zeros = and ones 
6)	Most modern digital systems operate using a Ans:-binary = logic 

7)	Binary uses a powers of Ans:-2 
8)	To convert a binary number to decimal Ans:- for each '1' in = the binary string, add 2n 
9)	The decimal equivalent of 0000000111 is Ans:-7 

10)	The l eft most bit i s typically called the Ans:- higher order = bit 
11)	Group of eight bits are called Ans:-bytes 
12)	The smal lest unit of information which a computer ca n understand = is Ans:- bit 

13)	Convert    the binary number 11.11 in to the decimal = Ans:  -3.75 
14)	( 2AC5.D)16 =3D ( ? )8 Ans:-10949. 8125 = 
15)	(623.77)8 =3D ( ?)16 Ans:- 193.FC 

16)	Going form binary to hexadecimal, grouping of four bits can be = obtained by Ans:-added as zero paddi ng on the MSB 

17)	Convert    172 in octal to decimal Ans:-122 
18)	The number of binary digits for each octal digit are = Ans:-3 

19)	Convert the binary number 001100111010 into octal number = Ans:-1472 

20)	Convert 15E hex to decimal Ans:-350 
21)	Convert the binary number 001100111010 to Hexadecimal number Ans: -33A 
22)	Octal is most useful when the binary sequence is multiples of = Ans: - three 

23)	Hexa decimal is most useful when the binary sequence is multiples = of Ans:-four 
24)	Taking the complement of a number t wice leaves the Ans:-number = as it is 

25)	To find out the complement of an n digit number the following = relation is valid one Ans:- r's complement =3D rn -number 
26)	In signed magnitude representation the sign is represented by the Ans:-MSB 

27)	In the signed magnitude representation the MSB of the binary = number is 1 then the number is Ans:- negative 

28)	In the signed magnitude representation -4 i s represented as Ans:-1100 
29)	Complementary representations are used to denote the = Ans:-negative of a given number 

30)	Find t he 1's compl ement of the bi nary number 0101 = Ans:-1010 
31)	Find t he 2's compl ement of the bi nary number 0101 = Ans:-1011 
32)	Obtain the 9's complement of the deci mal number 13469 = Ans:-86530 

33)	Obtain the 10's complement of the decimal number 90099 = Ans:-09901 

34)	The advantage of Gray code over the straight binary number = sequence is Ans: -only one bit changes when goi ng from one number to the = next 

35)	The standard binary code for the alphanumeric characters is Ans:-ASCII 
36)	The Format effectors of ASCII code are characters that = Ans:-control the layout of printing 

37)	To detect the errors during transmission of information from one = location to another, 

the following method is used Ans:-a parity bit is = added to the message
38)	The number of circuit elements required to represent a binary = number of n digits are Ans:- n 
39)	Computers can understand informati on only in the form of Ans:-binary 
40)	The number of distinct combi nations obtained from an n-bit binary = code is Ans:-2n 

41)	The bit combination of an n-bit code is det ermined from the count = in binary from Ans: - 0 to 2n-1 

42)	In BCD, the number of bits required to represent a number wit h 'n' = decimal digits is Ans: -4n 

43)	The sum of two BCD di gits produces a carry, then the foll owing = correction is required Ans:-add 0110 
44)	In BCD the minus sign is represented by Ans: -1001 
45)	The Excess-3 code for the decimal number 698 is Ans: -1001 1100 = 1011 

46)	The 9's complement of excess-3 code 0110 1100 1000 is = Ans:-1001 0011 0111 

47)	A register with 16 cells can st ore a binary number from Ans:-0 = to 216-1 

48)	When a key is struck, the control enters Ans:-an equivalent = ei ght-bit al phanumeric character code into the input register 

49)	The contents of a processor register are transferred i nto the = Ans:-  memory register 
50)	The number of bits stored in a regist er  with n cells are = Ans:-n 
51)	1+1 in binary logic is equal to Ans:-1 

52)	1+1 in binary arithmet ic is equal to Ans:-10 

53)	Whi ch of the following device possesses two stable states and is = capable of storing one bit of information Ans:-binary cell 

54)	A register is a group of Ans:-binary cells 

55)	The information from the input register is transferred into the Ans:-four least signi ficant cells of a processor register 

56)	The difference between binary arithmetic and binary logic is = Ans: -An arithmetic variable designates a number consist of many digits and y = l ogic variable is al ways either 1 or 0
57)	The multiplicative identity in Boolean al gebra is Ans:-1 

58)	In Boolean algebra t here is no subtraction or division operations = because Ans:-it does not have additive or multiplicative inverses 

59)	Reduce the Boolean expression A'C' + ABC + AC' t o three literals Ans:-AB + C' 
60)	The addit ive identity in Boolean algebra is Ans:-0 
61)	Switching algebra means Ans:-a two valued Boolean algebra 
62)	Switchi ng algebra can be represent ed by a el ectri c circuit of Ans:-bistable 
63)	x + x' is equal to Ans:-1 

64)	The Boolean expression xyz + x' y + xyz' can be rep resented with a = number of literals of Ans:- 
y 
65)	x + ( y . z ) =3D Ans:-(x+y) . ( x+ z) 

66)	The complement of a Boolean x' yz' + x'y'z is Ans:-(x + y'+ z) = (x + y + z') 
67)	The Boolean function for the following circuit shown in = Fig.1 
68)	= Ans:-x'+y 

70)	The generalized form of DeMorgan's theorem stat es that = Ans:-the complement of a function is				
obtained by interchanging AND and OR = operators and complementing each literal							
71)	According	to	duality	pri ncipl e	every	algebraic	expression	=	deducible	from	the	postulates	of	
Boolean																		
algebra remains valid if Ans:-the = operators and identity elements are interchanged							
72)	If the dual of an algebraic expression is desired then Ans:-interchange OR and AND						
operators and replace 1's by 0's and = 0's by 1's												
73)	A	Bool ean	function	described	by	an	algebraic	expression	consists	=	of	Ans:  -bi nary	variables,	
the																				
consta nts 0 and 1, and the logic = operation symbols											

74)	For a given value of the binary variables, the Bool ean function = can be equal to Ans: - either 1 or 0 
75)	The number of rows in the truth table of a Boolean function with n = variables is Ans:-2n 

76) A Boolean function can be    transformed from a n al gebraic expression =    into a circuit    composed
of
Ans:- logic gates

77)	Express t he Boolean function F=3Dxy+xz' in a Product of maxterm s Ans: F=3D(x+y+z)(x+y'+z)(x'+y+z)(x'+y+z') 

78)	Determine t he complement of the function F(x,y,z) =3DS ( = 1,3,6,7) Ans: - F(x,y,z) =3D (0,2,4,5) 
79)	Maxterm i s the compl ement of its corresponding = Ans:-minterm 

80)	Express t he Boolean function F=3DA+B'C in a sum of minterms Ans: F=3DA'B'C+AB'C+AB'C+ABC'+ABC 
81)	The number of minterms formed from n variables are Ans:-2n = 
82)	The Minterm is obtained from Ans:-an AND term of t he n = variables 
83)	The minterm is also called Ans:-standard product 

84)	The number of maxterms formed from n variables are Ans: -2n 

85)	The Maxterm is obtained from Ans:-an OR term of the n = variables 
86)	The maxt erm i s also call ed Ans:-standard sums 

87) Bool ean    funct ions    expressed    as a    sum    of    minterms    or    product of    = maxterms are    said to    be i n
Ans:- canonical form
88)	The equival ence function is also call ed Ans:-XNOR 

89)	Example of MSI devices is Ans:-counter 

90)	The following logic famil y is preferred for high component density = Ans:-MOS 
91)	The buffer is circuit whi ch produces Ans:-t he transfer = functi on 

92)	The expression in sum of products can be implemented with = Ans: -NAND gates only 

93)	The following circuit inverts t he logic sense of a binary variable = Ans:-inverter 
94)	The function that is 1 when the two binary variabl es are equal is = called Ans:- equivalence 
95)	The complement of Exclusive-OR is called Ans:-Equivalence 

96)	Negative logic system is defined as Ans:-Low =13level = represent logic 1 

97)	A positive logic AND gate can operate as a Ans:- negative = l ogic OR 
98)	Eight adjacent squares of k-map represent	a term of Ans:-one literal							
99)	In the	K-map any	two adjacent squares	differ	by Ans:-only	one =	variable	which	is	primed	in	
one square and unprimed in the other										
100) If a minterm in a square is covered by only one prime implicant, =	that prime impli cant is said		
to be Ans:-essential											
101) The Boolean expression for the following map is= Ans:-B'D' + A'CD'						
103)	The square in K-map represents a Ans:-min term 

104)	From K-map we can find a Boolean expression with a = Ans:-minimum number of terms and 
gates
105) The number of min terms for a three variable map is Ans:-8 =

106) The minterms of K-map are arranged in the form of a Ans:-gray = code107) The variable Y i n m5 and m7 whi ch are the = two adjacent squares in the K-map then Ans:-Y is primed in = m5 and unprimed in m7
108)	The sum of two minterms in adjacent squares of three variable map = can be simplifi ed to a 
Ans:-Single AND gate 
109)	The following is the adjacent cell for the cell 15 in five = variable K -map Ans:-31 
110)	The minimal Product of Sums expression for the following map is = 
111)	Ans:-f(w,x,y,z) =3D ( y + z)(y' + z')(w + x)(w '+ x') 

112)	The minimization of function expressed as product of sums is the = dual of that the Ans:-sum of product form 

113)	An incompl etely speci fied function containing k don't care = combinations actually corresponds t o a class of Ans:-2k distinct funct ions 

114)	Each don't care combination can be specified i n Ans:-either of = 0 or 1 

115)	Which of t he following is used to convert the sum of products to = product of sums Ans:-DeMorgan's 

116)	The logical sum of minterms associated with a Boolean function = specifies the conditi ons under which t he function is equal to Ans:-1 
117)	The don't care conditions can be used on a map to provide a Ans:-further simplification of the 

Boolean expressions
118)	A don=19t care minterm is a combination of variables whose l ogical = value is Ans:- not specified 
119)	To obtain a function in product of sums form from K -map the = following procedure is 
Applied Ans:-Mark the empty squares by 0's a nd = combine them into valid adjacent squares
120)	The NAND gate is also called as a Ans:-AND Invert 

121)	To convert a multilevel AND-OR diagram into a n all NAND diagram = the following is used Ans:- 

covert all OR gates to Invert-OR gates and = all AND gates to AND-Invert gates

122) To implement any Boolean function using NOR gates, it must be in = the form of Ans:- product of sums

123) The following symbol represent the gate called Ans:-Invert - OR
125)	Which of t he following gate is the uni versal gate Ans:-NAND = 
126)	The NAND gate is also called as a Ans:- Invert-OR 

127)	The NOR gate is also call ed as a Ans:-OR Invert 

128)	To implement any Boolean function using NAND gates, i t must be in = the form of Ans:-sum of products 

129)	Which of t he following gates are equal Ans:-AND-Invert and = Invert OR 

130)	To convert a multilevel AND-OR diagram into a n all NOR diagram the = following is used Ans:-covert all AND gates to Invert-AND gates and = all OR gates to OR-Invert gat es 

131)	The ECL NOR gates, when tied together, perform the Ans:-wired = OR l ogic 
132)	Wired logic provide a specific logic by connecti ng = Ans:-outputs from two gates 

133)	The logic function implement ed by t he following circuit is = Ans:-(AB +CD)' 

135) NAND or NOR gates allow the possibility of a wire connection = bet ween t he outputs of two gat es to provide a specific logic function. This type = of logic is called Ans:-wired logic
136)	The open collector TTL NAND gat es, when tied together, perform the = Ans:-wired- AND logic 

137)	The AND-NOR circuit can be equal to the followi ng circuit Ans:-NAND-AND 

138)	The OR-NAND circuit can be equal to the foll owing circuit = Ans:-NOR-OR 
139)	An AND-OR implementation requires an expression in the form of Ans:-Sum of product s 
140)	An OR-AND-INVERT implementation requires an expression in the form = of Ans:- Product of sums 
141)	The multiple variable exclusive -OR operation is defined as = Ans:-an odd function 

142)	An n-variable exclusive-OR function is an odd function defined as Ans:-the logical sum of 2n/2 

mint erms whose binary = numerical values have an odd number of 1s
143)	Which of t he following gate can perform t he Boolean function = xy'+x' y Ans: -XOR 
144)	The complement of excl usive-OR gate is Ans:-exclusive-NOR 
145)	Ans:-x' 

146)	Ans:- x 

147)	Ans:-1 
148)	Ans:-0 

149)	Ans:- 

150)	The code converter is a circuit that makes the two di fferent = binary code systems are 
Ans:- compatible 
151) The length of the various paths i n a multilevel combinational = circuit are Ans:-not    always
constant

152)	The output functions specified in the trut h tabl e gives the exact definition of the Ans:-combi nati onal circuit s 

153)	A combinational circuit consists of logic gates whose outputs at = any time are det ermined from the Ans:-present combination of input s 

154)	A combinational circuit consists of Ans:- logic gates, input = and output variables 
155)	A combinational circuit has a logic gates with Ans:-no feed = back paths 
156)	The following is used for logic simulation of combi national = circuit Ans:- verilog HDL 

157)	The Truth table defines the required relationship bet ween = Ans:-inputs and outputs 

158)	The input columns of a truth table for a combinational circuit are = obtained from Ans:- 2n binary numbers for the n input = variables.
159)	Every combinational circuit corresponds a Boolean function which = describes the circuit Ans:-logical behavior 

160)	An n-bit bi nary adder requires ......... number of full adders = with each output carry 

connected t o the ........ Ans:-n, input carry of the = next higher order full adder

161)	The over flow occurs when t he addition is perform , this problem = in di gital computers Takes care by using a Ans:-flip-flop 

162)	The longest propagati on delay time in the adder will be the time = it takes Ans:-the carry to propagate through the full adders 
163)	An overflow occurs if the t wo numbers added are Ans:-both = posit ive or both negative 

164)	The basic arithmetic operation in digital computers is = Ans:-addition 

165)	A combinational circuit that performs the addition of t wo bits is = called a Ans:-half adder 

166)	A combinational circuit that performs the addition of three bit s = is called a Ans: -full adder 
167)	The full adder can be implemented using Ans: -two half = adders 
168)	To perform addit ion of two n bit numbers, required full adders are = Ans: -n 

169)	The out put from the half adder is Ans:-sum =3D x'y +xy' , = carry =3Dxy 
170)	The out put form the full adder is = Ans:-S=3Dxy'z'+x'yz'+xyz+x'y'z , C=3Dxy+x'yz+xy'z 

171)	To construct a Binary Mul ti plier with J multipl ier bits and K = multiplica nd bits the following are required Ans:-(J x K ) AND gates and (J-1) = K- bit adders 

172)	The following is the circuit for the 
173)	= Ans:-2 x 2 bit Binary multiplier 
174)	In t he binary multiplier    the successive partial products are Ans:-shifted one position to the left 

175)	In t he Binary Multiplier the fi nal product is obtained from the Ans:-sum of the partial products 
176)	BCD adder consists of Ans:-two binary adders and logic circuit = wit h AND and OR gates 
177)	In t he Decoder t he    mi n term equivalent of the binary number = presentl y available i n the input lines 

represent t he Ans:-output whose value = is equal to 1
178) To generate a sum of min terms from n inputs and m outputs = combinational    circuit the followi ng is
used. Ans:- n-to-2n-line = decoder and m OR gates

179)	The combi nati onal circuit that converts binary information from n = input lines to a maxi mum of 2n unique output lines is called Ans:-Decoder 
180)	The 3-to-8- line decoder means Ans:-3 inputs are decoded into = 8 outputs 
181)	Which of the following device is used to convert binary code into = octal Ans: -3-to-8 line Decoder 
182)	The basic gat es required to construct a decoder are Ans:-AND = and NOT 
183)	In decoder the operation is controlled by the Ans:-enable = signals 

184)	To construct a 4 x 16 decoder how many 3 x 8 decoders are = required? Ans: -two 

185)	The Priority encoder produces a binary output code indicating = whi ch of the input lines requesting servi ce has the Ans:-highest priori ty 

186)	The operation of the priorit y encoder is such that , the input = having the highest priority will takeprecedence when t he Ans:-two or more = inputs are equal to 1 at the same time 

187)	To implement any Boolea n function of n variables wit h a = multiplexer requires Ans:-n-1 selection inputs, 2n-1 data = inputs 

188)	In an encoder , when one or more inputs are equal to 1 then it is indicated by setting Ans: -valid 
bit to 1
189)	The advantage of using a three state gates in a mult iplexer is Ans:-reducing loading effects 
190)	A digital circuit that performs the inverse operation of a decoder = is Ans:-encoder 

191)	Which of the following device is used to convert octal code int o = bi nary code Ans:-3- to-8 line Decoder 

192)	An encoder has Ans:-2n i nput lines and n out = lines 

193)	An encoder circuits must establish an input priori ty to ensure = t hat Ans:-only one i nput is active at any given time 

194)	The number of selection lines required for a 2n input = lines multiplexer is Ans:-n 
195)	A multiplexer is also called a Ans:-data selector 
196) In what way one module definition of verilog HDL can be = incorporated in another    module
Ans:-instantiating
197)	What is the syntax for a output vector D with four bits 0 through = 3 in verilog HDL Ans: -output[0:3] D 

198)	How the unknown and high impedance are represented in verilog HDL = gate level model Ans:-x 
and z

199) The gate-level modeling in Verilog HDL describes the circuit by =    specifying the Ans:- gates and

how they are connected with each other

200)	The data flow modeling in Verilog HDL describes the circuit by = specifying the Ans:- continuous assignment statements 

201)	The behavioral modeling in Verilog HDL describes the circuit by = specifying the Ans:- procedural assignment statements 
202)	The number of operator types in verilog HDL are Ans: -30 

203)	In verilog HDL data flow model the 2-to-1 line multiplexer wit h = data inputs A and B, select input S, and output Y i s described by = Ans:-assign Y=3D(A & S) | (B & J S) 
204)	The behavioral modeling of verilog HDL represents digital	circuits = at a Ans: - functional and	
algorithmic level		
205)	The gate level modeling of verilog HDL represents digital circuits = at a Ans:-gate level